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Chip (and chip family) names without digits

name cat description manufacturer
ADSST-AEC dsp Fixed Point DSP Acoustic Echo Cancellation (AEC) algorithm chipset AD
ADSST-AEC-SPA dsp Fixed Point DSP Acoustic Echo Cancellation (AEC) algorithm chipset from Signal Processing Associates AD
ADSST-AGC dsp Fixed Point DSP Digital Automatic Gain Control algorithm chipset from Signal Processing Associates AD
ADSST-AUD-DD dsp SHARC* Floating Point DSP-based Dolby Digital chipset AD
ADSST-AUD-HDCD dsp SHARC* Floating Point DSP with HDCD Decoder/Post Processing Filter algorithm chipset AD
ADSST-AUD-MPEG dsp SHARC* DSP MPEG II Audio Decode algorithm chipset AD
ADSST-AUD-THX dsp SHARC* Floating Point DSP THX Decode algorithm chipset AD
ADSST-AUD_PROL dsp SHARC* Floating Point DSP Dolby Pro-Logic algorithm chipset AD
ADSST-CID dsp Fixed Point DSP Caller Identification algorithm chipset AD
ADSST-CS dsp Extended Csound Development Environment AD
ADSST-DAM dsp Fixed Point DSP Digital Answering Machine Application and Reference Design AD
ADSST-DTMF dsp Fixed Point DSP DTMF Decode and DTMF Encode algorithm chipset AD
ADSST-LEC dsp Fixed Point DSP LEC algorithm chipset AD
ADSST-MGSM dsp Fixed Point DSP MGSM Speech Code, 5.0 Kbps algorithm chipset AD
ADSST-MPEG dsp Fixed Point DSP MPEG Audio I algorithm chipset AD
ADSST-TONE_DET dsp Fixed Point DSP Tone Detection algorithm chipset AD
ADSST-VAD dsp Fixed Point DSP Voice Activity Detection algorithm chipset AD
ADSST-VOICDIAL dsp Fixed Point DSP Voice Dialer algorithm chipset AD
ALCOR chipset (=2117x) Support chipset for the 21164. Provides a memory controllers and 32/64-bit PCI host bridge for it's CPU. It consists of 5 chips (4, 64-bit data slices (Data Switch, DSW). 208-pin PQFP and 1 control (Control, I/O Address, CIA) - a 383 pin plastic PGA). It provides a DRAM controller (256-bit memory bus) and a PCI interface. It also does all the work required to support an external Bcache and to maintain memory coherence when a PCI device DMAs into (or out of) memory. DEC*
ALCOR2 chipset (=2117xA) Support chipset for the 21164A, similar to ALCOR. DEC*
APECS chipset (=2107x) Support chipset for the 21064/21064A. Provides a memory controller and a 32-bit PCI host bridge for it's CPU. It consists of 6, 208-pin chips (4, 32-bit data slices (DECADE), 1 system controller (COMANCHE), 1 PCI controller (EPIC)). It provides a DRAM controller (128-bit memory bus) and a PCI interface. It also does all the work to maintain memory coherence when a PCI device DMA*'s into (or out of) memory. DEC*
ARC core (Argonaut RISC Cores) - More, See: www.arccores.com/ and www.atinucleus.com/ Now sold by Accelerated Technology.
ARM core See 86600 86610, Family ARM
Alpha mpu See 21064, 21066, 21068, Family DEC*, Mitsubishi, Samsung
Athlon mpu Official name of AMD's successor to the K6, earlier codenamed K7. At it's arrival in 1999 the highest tacted processor around (700 Mhz) AMD*
Butterfly mpu Family ARM
COMANCHE system System controller in the APECS chipset DEC*
COP mcu See 8, 820, 880, 888 NS*
Capstone mpu See MYK-80 Cryptographic processor (ARM6), Family ARM
Clipper mpu But later also a Cryptographic processor (ARM6), Family, see MYK-78E, MYK-78T, MYK-77. ARM
Clipper mpu MCU from Fairchild, later adopted by workstation manufacturer Intergraph after Fairchild was bought by NS. Fairchild*
Cobra video XGA Graphics controller Chip IBM*
Coldfire mcu An 68000 instruction set executing MCU that Motorola calls RISC. Family Motorola
Deerfield mpu 3th successor of Intel's Merced. It will probably be a more economical version of the Merced, McKinley or Madison. Intel
EPIC bus PCI controller in the APECS chipset DEC*
GVSC mpu See 1750 IBM
HFC-S PCI isdn ISDN controller (including S/T interface, HDLC controllers for B-channels and D-channel, PCI bus interface, PCM30 interface) (HFC-S PCI is usable as "PCI to 8 bit generic" bridge, too) (3.3V and 5V) Cologne*
HFC-S+ isdn ISDN controller (including S/T interface, HDLC controllers for B-channels and D-channel, microprocessor interface, PCM30 interface) (3.3V and 5V) Cologne*
HFC-SP isdn ISDN controller (including S/T interface, HDLC controllers for B-channels and D-channel, microprocessor interface, ISA-PnP bus interface, PCMCIA bus interface, PCM30 interface) (3.3V and 5V) Cologne*
HPC* mpu (High Performance Computer), 16-Bit MCU family, See 46003, 46083, 46100, 46164, 46400 NS*
Hobbit mpu 32-bit Stack Oriented RISC CPU, discontinued unfortunately AT&T/NCR
IC-VX driver Line Driver, 3-Channel, Differential IC-Haus*
Lontalk bus See 3120, 3150 Echelon*
MIPS mpu See 10000, 3000, 4000, 4200, 4400, 4600, 8000 MIPS
MISC mpu (Minimal Instruction Set Computer), Forth oriented processor, see F21 and www.m-i-s-c.net/ Ultra Technology
MWave dsp One of the first DSP architectures, Family IBM*
Madison mpu Faster version of the McKinley using 0.13 micron technology. Intel*
Mantis mpu See the Family ARM
McKinley mpu The first successor of the Merced: Using 0.18 micron copper technology and faster than 1 Ghz, according to Intel on 19981014. Intel*
Merced mpu The still long awaited 64 bits processor by Intel. Rumour has it that it's release is so much delayed that it's successor will be introduced earlier then the Merced itself... ;-). Merced will probably use 0.18 micron non-copper technology. It's introduction is now (=199812) expected in 1999q4. The successors are planned to be the McKinley, Madison and Deerfield. www.microprocessor.sscc.ru/Merced/ (Critical comparison with existing processors and DSP's). Intel*
MicroSparcII mpu Sparc processor from SUN SUN
Neptune chipset Chip set to make PC with (Intel?, Sis, VLSI, Opti ..) (?). 83430NX chipset with the 82434 PCMC (PCI/Cache/Memory controller). Intel's previous generation Pentium/PCI chipset. Supports Pentiums to 100 MHz only, standard DRAM only (not EDO), standard cache (not pipeline burst), approx. 45 MB/sec PCI throughput. Only two advantages over the Triton chipset: supports multiprocessing (dual Pentiums) and prefetch reads from PCI slaves. Source: PCI-FAQ. Intel
Neuron bus See 3120, 3150 Echelon*
Orion chipset Pentium Pro chipset, See 82450. Intel?
P5 mpu Pre-release code name for the i586, now known as Pentium, Family Intel*
P6 mpu Pre-release code name for the i686, Family Intel*
P7 mpu Pre-release code name for the i786, Announcement, Family Intel*
P8 mpu Pre-release code name for the i886, Family, Intel*, HP*
PACE mpu See 1750 Performance Semiconductor
PIC mcu See the Family Microchip
Pentium mpu See also 80586, Family, Family Intel
PowerPC mpu See 601, 602 (?), 603, 604, 620, Family Motorola, IBM, Apple
RubyII mpu VPS10101 (ARM6) MCU, Family ARM
SHARC* dsp Family AD*
SSCRFCEDW radio Radio Frequency (RF) Transciever IC*, CEBus Compliant Intellon*
Sparc mpu See 7600, 7601, 7603, 7608, 7153, 7181 and .. (?), Design-experiences-with SUN*
Spider mpu Family ARM
StrongArm mcu See SA-110, MCU, 230 V2.1 Dhrystone MIPS (200MHz at 2.00V), Family ARM
Super8 mcu See 8800, 8801, 8820, 8822, 8-Bit MCU (=Z8+), Pins, Regs, Incl-f, Incl-s Zilog*
SuperSparcII mpu Sparc processor SUN
Transputer mpu See 212, 414, 800, 9000 etc. I-set, About Newslist, www.afm.sbu.ac.uk/transputer/ INMOS*
Triton chipset Chip set to make PC with. 83430FX chipset with the 82437 System controller. Intel's latest Pentium/PCI chipset. Supports Pentiums of all speeds, EDO memory, pipeline burst cache and 100 MB/sec PCI throughput. Source: PCI-FAQ. Intel?, Sis, VLSI, Opti?
TwoChipPIC mcu MIPS based processor for PIC's/PDA's and related devices, includes fax/data modem software Philips*
UltraSparc mpu Sparc processor from SUN. Sun Microsystems, Inc. announced (199811) the availability of samples of the 400-MHz version of the UltraSPARC-II microprocessor and the plans for the 450-MHz version to be available in the Spring of 1999. www.sun.com/smi/Press/sunflash/9811/sunflash.981102.2.html SUN
VGA video Several VGA-Chipsets: Regs many
Xeon mpu Advanced 450 MHz Pentium II. Intel
Z8 mcu See 8600, 8601, 8603, 8604, 8606, 8607, 8608, 8610, 8611, 8621, 8630, 8631, 8640, 8671, 8681, 8691, 8-Bit MCU Zilog
CompactRISC mpu a 16 bit Embedded applications RISC family, www.national.com/appinfo/compactrisc/ NS*
Forth/Stack mcu www.ultratechnology.com/chips.htm Ultra
HFC-S USB isdn,telecom ISDN controller (including S/T interface, 4 HDLC controllers for B-channels and D-channel, USB interface, PCM128, PCM64, PCM30 interface) (the USB protocol is implemented in hardware) (3.3V and 5V) Cologne*
HFC-S active isdn,telecom ISDN microprocessor system on a single chip (SoC) (based on a powerful ARM7 RISC processor, including 16 kByte SRAM* (0 wait states), a S/T interface, HDLC controllers for B-channels and D-channel, two integrated CODECs, a full speed USB-interface and a standard RS232* interface) Cologne*
HFC-S mini isdn,telecom ISDN controller (including S/T interface, 4 HDLC controllers for B-channels and D-channel, microprocessor interface PCM128, PCM64, PCM30 interface) (3.3V and 5V) Cologne*
Itanium mpu Final name for Intel's 64 bit Merced processor Intel*
MISC mpu see www.m-i-s-c.net/ Ultra Technology*
Nios mpu soft core embedded processor, with new simultaneous multi-master bus architecture to optimize data flow in high-bandwidth applications, easy integration of user-defined processor instructions to accelerate program execution, world-class debugging solutions using an on-chip debug peripheral for real-time debugging and software trace and SDRAM* interface and memory controller peripherals, data Altera*
SA... see NE...
XScale Intel's successor of the StrongARM. Intel bought the StrongARM from DEC Intel
capesr www.icst.com/pdf/capesr.pdf ICS*
mstrrep www.icst.com/pdf/mstrrep.pdf ICS*
sjmap www.icst.com/pdf/sjmap.pdf ICS*
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