6850
UART register usage
19871016/wjvg

0  control/status
   w ......00  counter/1
   w ......01  counter/16
   w ......10  counter/64
   w ......11  master reset
   w ...000..  7 bit, even parity, 2 stopbit
   w ...001..  7 bit,  odd parity, 2 stopbit
   w ...010..  7 bit, even parity, 1 stopbit
   w ...011..  7 bit,  odd parity, 1 stopbit
   w ...100..  8 bit,   no parity, 2 stopbit
   w ...101..  8 bit,   no parity, 1 stopbit
   w ...110..  8 bit, even parity, 1 stopbit
   w ...111..  8 bit,  odd parity, 1 stopbit
   w .00.....   rts,  dis/en xmit interrupt
   w .01.....   rts,  en/dis xmit interrupt
   w .10.....  -rts,  dis/en xmit interrupt
   w .11.....   rts,  dis/en xmit intrpt, xmit brk-level
   w 1.......   en/-dis receive interrupt
   r .......1  rcve data reg full
   r ......1.  xmit data reg empty
   r .....1..  -data carrier detect (or has been down)
   r ....1...  -clear to send
   r ...1....  framing error
   r ..1.....  receiver overrun
   r .1......  parity error
   r 1.......  interrupt request
1  data
   r  receive
   w  transmit
 
end