6844
DMA register usage
19871016/wjvg

00  adres0   (rw)
02  counter0 (rw)
04  adres1   (rw)
06  counter1 (rw)
08  adres2   (rw)
0a  counter2 (rw)
0c  adres3   (rw)
0e  counter3 (rw)
10  control0
11  control1
12  control2
13  control3
    rw .......1  output/-input
    rw .....00.  halt steal
    rw .....01.  halt burst
    rw .....10.  tsc  steal
    rw .....11.  illegal
    rw ....1...  address down/-up
       ..xx....  not used
    r  .1......  dma busy
    r  1.......  dma end
14  priority control
    rw .......1  enable drq0
    rw ......1.  enable drq1
    rw .....1..  enable drq2
    rw ....1...  enable drq3
       .xxx....  not used
    rw 1.......  rotating/-fixed priority
15  interrupt control
    rw .......1  enable irq0
    rw ......1.  enable irq1
    rw .....1..  enable irq2
    rw ....1...  enable irq3
       .xxx....  not used
    r  1.......  irq end
16  data chain
    rw .......1  data chain enable
    rw .....00.  select data chain0
    rw .....01.  select data chain1
    rw .....10.  select data chain2
    rw .....11.  select data chain3

end